THE RAPIDLY INCREASING design process interactions of the 65 nm and future device generations will present a considerable challenge to logic manufacturers. The main lithographic issues are decreasing focus budgets caused by high numerical aperture (greater than 0.8) lenses, and increased sensitivity to exposure dose and reticle critical-dimension (CD) errors caused by lower lithographic linearity. Extrapolating the known linearity loss and the yield issues observed in the 130- and 90-nm generations points to the likelihood of significant yield loss at the 65-nm generation. The reason for the reduced yields is widely attributed to pattern-specific issues, where traditional physical design rules are increasingly unable to guarantee high yield for a device. Nonoptimal points in the increasingly complex lithography process space inevitably interact with difficult physical-design locations to create semi-random pattern failures. Therefore, designers will need to employ new strategies as part of the physical-design flow to solve these intertwined patterning design issues. The steps that create physical shape data in a typical logic device design-to-reticle flow are cell layout, place and route, tapeout, OPC or RET, data fracture, and reticle build. Here, we define OPC as the transformation of reticle data to compensate for lithographic and process distortions so that the final wafer pattern is as close to the target pattern--the designed layout--as possible. We define RETs as the general class of transformations for reticle data that aim to improve the patterning process window; therefore, OPC is a subset of RET. DFM is traditionally considered to be implemented at the cell layout or routing stages of this flow. Examples include the optimization of a layout based on critical-defect area, the addition of redundant contacts and vias, wire spreading, upsizing of metal landing pads, and the addition of dummy metal tiles to improve the planarity after chemical-mechanical planarization (CMP). We presented a detailed analysis of these techniques in an earlier work. In contrast, this article analyzes the possibility of extending these traditional methods into the OPC stage and introduces new post-tapeout RET methods for improving printability.
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