TIME-TO-MARKET IS ONE of the major constraints of system-on-chip (SoC) designs. Project teams usually rely on standard IP blocks that are reused across different products to achieve quick turnaround time. Therefore, efficient system-level interconnect solutions that can seamlessly glue different IP blocks, become an integral component of SoC designs. However, if not designed carefully, deadlocks and livelocks in a system-level interconnect can present significant challenges to quick SoC integration. Distributed nature of the system-level interconnect and tricky interaction between many IP blocks make this problem hard to understand and debug. This is in strong contrast to other functional problems, which may often be narrowed down to a few blocks in the design that are well understood by both the implementers of the block, as well as the system architects. Furthermore, deadlock problems at the system level are hard to fix after they are found: to fix them cheaply requires sacrificing performance by limiting concurrency, and to fix them properly may require altering many blocks.
展开▼
