POWER DISSIPATION HAS become the chief performance limitation in modern microprocessors, thus triggering a flurry of research activities on low-power design techniques. One of the most effective ways to curb chip power is to integrate larger cache memories to improve microarchitectural performance at only a modest increase in CV2f power. As a result, the past decade has seen a precipitous increase in the amount of on-die embedded memory. In state-of-the-art designs, approximately half the chip area can be devoted to cache memory. For example, Intel's 8-core Nehalem processor has 24 Mbytes of shared L3 cache based on SRAM cells, while IBM's Power7 processor has a 32-Mbyte L3 cache built in an embedded DRAM (eDRAM) technology. The need for robust, high-density embedded memories is projected to grow as designers continue to seek power-conscious ways to improve chip performance. The unique challenges and opportunities associated with embedded memory design make it an important area of research in extremely scaled technologies.
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