Data Reorganization and Prefetching of Pointer-Based Data Structures

摘要

FPGAS CONSIST OF thousands of small configurable logic blocks and hundreds of internal storage blocks that can implement virtually any combinatorial or sequential logic. With FPGAs, designers can implement dedicated functional units to compute sophisticated arithmetic or application-specific operations that are not directly implemented in traditional architecture systems. Still, despite their tremendous internal data and computational bandwidth, FPGAs are limited by the same memory-bandwidth bottleneck (see the "Related Work on Memory Bottlenecks" sidebar) that plagues traditional systems. Worse, given their clock-rate handicap, getting the data into an FPGA is an order of magnitude slower than getting it into a traditional, computing system. The absence of cache storage further exacerbates this handicap.