HOW WILL 3D integration change IC testing? That was the debate in this ITC 2010 panel and which, since the panel was standing-room only, is clearly a hot topic in the industry. A set of industry experts debated the key questions facing 3D testing. Is existing design-for-test (DFT) and associated test methods sufficient? Do we have to probe and test all through-silicon vias (TSVs) at wafer level? What are the test requirements for the dies before being integrated on the 3D assembly? Are existing probing technologies sufficient for 3D test? (If not, what is being developed to fill this gap?) What are the important yield and thermal considerations? In concluding the debate, each panelist described the key challenges for implementing a 3D application. To start the session, Dean Lewis, a researcher from Georgia Tech, presented a target application developed by Georgia Tech: a 3D massively parallel processor with stacked memories. This device includes five layers including 64 processor cores, a large SRAM, and three layers of an eDRAM subsystem. The DFT architecture is a 3D custom adaptation of the 1149.1 standard that enables prebond test of each layer. TSVs are tested after bonding, when they can be treated as any other net. The 3D technology uses a 1.2-(mu)m TSV from Tezzaron.
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