Design and test on chip for EMC

摘要

THE IEEE COMPUTER Society's Test Technology Technical Council (TTTC) organized this panel as part of the 2006 EMC Europe International Symposium on Electromechanical Compatibility (http://www.emceurope2006. org), held in Barcelona, Spain, 4-8 September 2006. The panel addressed the recent explosion of the portable-electronics market and the increasingly hostile electromagnetic (EM) environment in which these systems must operate. This scenario has intensified the need to include strict noise-immune parameters in design and test methods of SoCs. Focusing on the design of embedded systems for harsh environments, this panel tried to satisfy such a need. The panel addressed three challenging issues: (1) How do we design new reliable products with enhanced environmental awareness? In the field of test, design and subsequent test have given way to DFT techniques. Consequently, system dependability has driven the need for online testing for transient faults such as single-event upsets (SEU). It might be possible to reuse such on-chip resources for design for EMC (DF_EMC). The design, test, and EMC communities need to work together to minimize the cost of DF_EMC.